module top_module (
    input clk,
    input areset,
    input x,
    output z
); 

    parameter A = 1'b0;
    parameter B = 1'b1;
    
    reg		state;
    reg		next_state;
    
    always @(posedge clk or posedge areset) begin
        if(areset) begin
            state <= A;
        end
        else begin
            state <= next_state;
        end
    end
    
    always @(*) begin
        case(state)
            A:	next_state = x ? B : A;
            B:	next_state = B;
        endcase
    end
    
    always @(*) begin
        case(state)
            A:	z = x;
            B:	z = ~x;
        endcase
    end
    
endmodule
